1. Field of the Invention
The present invention relates primarily to chip size semiconductor packages comprising semiconductor integrated circuits, particularly solid-state image sensors such as CCD and CMOS, and a method of manufacturing these packages.
Priority is claimed on Japanese Patent Application No. 2003-304848, filed on Aug. 28, 2003, and Japanese Patent Application No. 2003-419613, filed on Dec. 17, 2003, the contents of which are incorporated herein by reference.
2. Description of Related Art
Conventionally, when mounting semiconductor integrated circuits, particularly solid-state image sensors including CCD (Charge Coupled Device) or CMOS (Complementary Metal-Oxide Semiconductor), the method shown in FIG. 13 is typically used. That is, in this mounting method, a solid state image sensor 1001 is placed in a receptacle 1002 made of ceramic or resin or the like, wire bonding 1003 is performed between the sensor and a lead frame (not shown) to provide an electrical connection, and a glass lid 1004 is then fitted to provide a hermetic seal. Reference numeral 1005 indicates an outer lead.
Recently, with the progress in miniaturization, particularly in portable devices, there has been a demand for smaller housings and internal circuit boards. Of course, the demand for such miniaturization also exists for semiconductor elements, which are one of the surface mounted components which make up a circuit board. Furthermore, the same miniaturization is demanded of solid-state image sensors, which are a form of semiconductor element.
In order to meet this demand for miniaturization of semiconductor elements, research and development is being actively pursued in the field of Chip Size Packages (referred to as “CSP” below). Above all, in recent years the development of wafer level CSPs is being actively pursued with an object of providing smaller, lighter and thinner packages.
As described in the specification of Japanese Patent No. 3313547, a wafer level CSP typically has resin and rewiring on the silicon wafer element surface, and also has metal posts or solder balls for providing solder connections, arranged in the desired locations on the silicon wafer element surface.
In Japanese Unexamined Patent Application, First Publication No. 2001-351997, a CSP is proposed in which the rewiring and the solder balls and the like are placed on a semiconductor substrate surface which is opposite to that on which the semiconductor element is formed.
In National Publication of Japanese Translated Version No. H09-511097 (PCT publication No. WO95/19645), it is disclosed that by making use of partial notches provided in the silicon substrate, the metal wires which extend from the electrode pads on the surface where the element is formed can be provided on the opposite surface.